Computer Component
64 questions · Fundamental Engineering · 1–50
The figure shows the storage sequence of instructions fetched by a processor. Which of the following corresponds to a?
Which of the following is an appropriate CPU operation associated with cache memory?
What is the theoretical maximum data transfer rate in MB/s for the external bus of a 64-bit microprocessor that uses a 64-bit external data bus driven by a 64 MHz input clock? Here, it takes 4 input clock cycles to complete 1 bus cycle.
There exists a main process and the two (2) interrupt processes A and B, as shown in the table below. Multiplex interrupts are permitted. When interrupts A and B occur with the timing shown in the diagram below, how many milliseconds (ms) can the main process use the CPU during the time period between 0 ms and 5 ms? Here, the overhead from calling an interrupt process and resuming from it can be ignored.
When an HDD has the specifications shown in the table below, what is the average access time for the HDD to transfer 16 kB of data in milliseconds (ms)? The average access time is calculated as the sum of the average seek time, controller overhead, rotational latency, and transfer time. Other overheads can be ignored. Here, 1 MB = 1,024 kB.
Which of the following is an appropriate description of a 3D printer’s function?
For a CPU with a clock frequency of 800 MHz, where one instruction is executed in an average time of 4 clock cycles, what is the CPU performance in MIPS?
When a CPU has a special register used in push and pop instructions, which of the following is an appropriate term for this register?
The table below shows the access times for the cache memory and main memory in systems A and B. Which of the following is the approximate hit ratio of the cache memory, when the effective access time and the cache memory hit ratio are the same for systems A and B?
When it takes 10 ns to copy a byte, which of the following is the approximate time (in ms) to copy the data for a 1024 × 768-pixel graphics screen with 24-bit color? Here, any overhead time for copying can be ignored.
What is the approximate performance of a CPU in MIPS, when the instruction mix of the CPU is shown in the table below? Here, the CPU does not use a pipeline architecture.
When the CPU needs data, it first accesses the cache memory. When the data is not available in the cache memory, the CPU accesses the main memory. If the miss ratio is 0.2 and the access times for cache memory and main memory are as shown below, what is the approximate average memory access time in ns for the CPU? Here, there are only cache memory and main memory for the CPU, the access time for main memory includes the time to confirm whether the data is available in cache memory, and the overhead time for the cache management can be ignored.
There are two microprocessors: a 32-bit CPU capable of executing each of 32-bit, 16-bit, and 8-bit long instructions in 1 cycle, and a 16-bit CPU capable of executing each of 16-bit and 8-bit long instructions in 1 cycle. Additionally, the 16-bit CPU can execute a 32-bit long instruction in 2 cycles. When the appearance ratio of 32-bit long instructions is 40%, of 16-bit long instructions is 40%, and of 8-bit long instructions is 20% respectively, what is the percentage improvement in total execution time with the 32-bit CPU compared to the 16-bit CPU? Here, both the 32-bit and 16-bit CPU operate at the same clock speed and have the same performance except for the executable instruction length in 1 cycle.
When an HDD has the specifications below, what is the average access time for an HDD to transfer 1 MB of data in ms? Here, the average access time can be calculated as the sum of the average seek time, controller overhead, rotational latency, and transfer time. Other overheads can be ignored.
Which of the following is the port that can theoretically connect up to 127 peripheral devices, controlled by a PC?
In a CPU, which of the following is a special register that contains the address of the next instruction to be fetched?
Which of the following is a computer architecture in which a processor executes the same instruction on multiple data?
ECC is used for error detection and correction in memory. When n+2 redundant bits are required for a data bus having a width of 2n bits, what is the number of redundant bits that are required for a data bus having a width of 128 bits?
Which of the following is the technique that minimizes the number of write operations to the main memory by updating the data only in the cache memory and updating into the main memory later?
A printer prints 400 characters per second. The printer uses interrupt-driven I/O and each character printed requires an interrupt that takes 50 microseconds. What percentage of the printer's CPU is available to do other work during printing? Here, other overhead time for the CPU can be ignored.
There is a 32-bit microprocessor with 32-bit external data bus, driven by 64 MHz input clock, and the processor takes 8 input clock cycles to complete 1 bus cycle. What is the theoretical maximum data transfer rate in megabytes per second (MB/s) for the external data bus of the processor?
There is a computer that has an average instruction execution time of 20 nanoseconds. What is the performance of this computer in MIPS?
There is a disk drive that has a capacity of 8 GB. The drive has five (5) platters with two (2) surfaces: 10,000 tracks per surface and 200 sectors per track. How many bytes are in each sector? Here, 1 GB is 1,000,000,000 bytes.
Which of the following is a memory device that stores programs or data in factories and only has the read operation for the stored programs or data?
Which of the following is the average cycles per instruction (CPI) of a computer that can execute 1 billion instructions per second at a clock rate of 2.4 GHz?
What is the approximate average access time in milliseconds (ms) of a magnetic disk with the specifications shown in the table below? Approximate average access time is the sum of average seek time, track-to-track seek time, and average rotational delay. Here, the controller overhead can be ignored.
Which of the following is the list that contains A through D sorted starting with the shortest effective access time of the main memory?
Which of the following is a special register that contains the address of the next instruction to be fetched?
Which of the following is the performance of a CPU in MIPS when the instruction mix of the CPU is as listed in the table below? Here, the CPU does not use a pipeline architecture.
Which of the following is a computer system or architecture where the CPU sequentially reads and executes the programs that are stored in the main memory?
Which of the following is an appropriate term for a special register that contains the address of the next instruction to be fetched?
In memory systems, when data is detected in the cache, it is known as a hit. When data is not detected in the cache, it is read from the main memory and is known as a miss. Which of the following is the approximate hit ratio for the specifications in the table below? Here, effective access time is calculated as the weighted average of hit time and miss time, and other overhead is ignored.
Which of the following is a computer architecture where each instruction is divided into multiple stages (e.g., fetch, decode, and execute) in the processor and multiple functional units execute two or more instructions in parallel by slightly shifting execution stages of the instructions?
Which of the following is a connection method that is referred to as a daisy chain?
A processor takes 15 seconds to run an application compiled with an old compiler. A new compiler was released. The same application compiled with the new compiler executes fewer instructions by 40%, but the average clock cycles per instruction (CPI) is increased by 10%. How many seconds does it take for the same processor to run the same application compiled with the new compiler?
Which of the following is a characteristic of a RISC processor when it is compared with a CISC processor?
Which of the following is an appropriate characteristic of SRAM compared with DRAM?
Which one of the following serial transmission methods is used in asynchronous data communication?
When the least recently used (LRU) method is used for swapping a block between cache memory and main memory, which of the following is a block in cache memory to be replaced?
A CPU has a clock frequency of 2.0 GHz. When the instructions consist of three types, as shown in the table below, what is the approximate CPU performance in MIPS?