ITPEC FE Subject A April 2026 Question 10
ITPEC FE Subject A April 2026 — Question 10 of 60
When a cache miss occurs, the CPU fetches data from the main memory.
Cache memory holds recently used data close to the CPU:
- •Cache hit — the data is in the cache, so it is read from there and main memory is not touched
- •Cache miss — the data is absent, so the CPU goes to main memory and usually copies the block into the cache for next time
Answer (d)
Why not others:
- (a) — a hit is served from cache; ROM stores firmware and is unrelated to caching
- (b) — going to main memory on a hit would defeat the entire purpose of a cache
- (c) — a miss means the data is not in cache, so it cannot be fetched from there
Key rule: Hit means served by cache, miss means served by the slower level below it. Any option pairing hit with main memory, or miss with cache, is inverted.
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