ITPEC FE Morning October 2019 Question 13
ITPEC FE Morning October 2019 — Question 13 of 80
Cache Memory Write Policies — identify correct behavior of cache memory.
Two main write policies exist:
- •Write-through — data is written to both cache and main memory simultaneously
- •Write-back — data is written only to cache; main memory is updated when the cache line is evicted
Why not others:
- (a) Cache bridges the speed gap between CPU and RAM, not between physical and virtual memory
- (b) The speed gap between CPU and RAM is growing, making cache more necessary, not less
- (c) Cache miss handling is done by hardware automatically, not by the program — cache is transparent to software
Key rule: Cache is a hardware-managed, transparent speed buffer between CPU and main memory. Write-through vs write-back is a classic exam topic.
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