ITPEC FE Morning October 2019 Question 13

Cache writes are either write through or write back — memory is updated on every write, or only when the modified block leaves the cache.

• •Write through: each write goes to the cache and to main memory together. Memory is always up to date, but every write costs a memory access.
• •Write back: a write changes only the cache block and marks it modified. The block is copied to main memory when it is replaced, so many writes to one block cost a single memory write.

Answer (d)

Why not others:

• •(a) — cache fills the speed gap between the CPU and main memory; the capacity gap is what virtual memory, backed by disk, addresses
• •(b) — processors have become faster than memory at a greater rate, so the gap has widened and CPUs now use several cache levels
• •(c) — a cache miss is handled by hardware, invisibly to the program; an interrupt followed by a software transfer describes a page fault in virtual memory

Key rule: Cache is managed by hardware to hide main-memory latency and is transparent to programs; designs differ in write policy and hit ratio.

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