ITPEC FE Morning April 2020 Question 12

UART — the Universal Asynchronous Receiver/Transmitter frames each character with start and stop bits instead of sharing a clock.

In asynchronous transmission the sender and receiver share no clock. The idle line sits at 1; a start bit (0) announces a character, the receiver samples the data bits at the agreed baud rate, and one or more stop bits end it. The receiver resynchronises on every start bit, so small differences between the two clocks never build up.

Answer (d)

Why not others:

• •(a) I²C — synchronous: the master drives a clock line (SCL) that times every bit on the data line (SDA)
• •(b) PCI Express — a high-speed expansion bus that sends continuous encoded packet streams, with the receiver recovering the clock from the signal; there is no start/stop framing per character
• •(c) SPI — synchronous: the master drives a clock line (SCLK) that times every bit on the data lines

Key rule: A serial link is synchronous if bit timing comes from a clock, on its own line or embedded in the signal, and asynchronous if each character carries its own start and stop bits.

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