ITPEC FE Subject A April 2026 Question 11
Topic: Computer Component
What is the theoretical maximum data transfer rate in MB/s for the external bus of a 64-bit microprocessor that uses a 64-bit external data bus driven by a 64 MHz input clock? Here, it takes 4 input clock cycles to complete 1 bus cycle.
Explanation
128 MB/s — convert the clock to bus cycles, then multiply by the bus width in bytes.
- •Bus cycle rate: 64 MHz with 4 clock cycles per bus cycle gives 64 ÷ 4 = 16 million bus cycles per second
- •Bus width: 64 bits = 8 bytes per bus cycle
- •Transfer rate: 16 × 8 = 128 MB/s
Answer (b)
Why not others:
- •(c) 512 — uses the raw 64 MHz clock as the bus cycle rate, 64 × 8, ignoring that one bus cycle takes 4 clock cycles
- •(a) 12.8 and (d) 1280 — a factor-of-ten slip either side of 128
Key rule: Divide the input clock by the clock cycles per bus cycle before multiplying, and convert the bus width from bits to bytes.
Computer Component · AI-written, may contain errors
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