ITPEC FE Subject A April 2026 Question 9

Source exam: ITPEC FE Subject A April 2026Topic: Computer Systems & Hardware

ITPEC FE Subject A April 2026 — Question 9 of 60

Instruction register — the stage between main memory and the instruction decoder.

The fetch-execute cycle runs: the address in the program counter selects an instruction in main memory, the instruction is copied into the instruction register, and the decoder then interprets it. The box marked a sits exactly in that position.

Answer (c)

Why not others:
- (a) Accumulator — holds operands and arithmetic results, not the instruction being decoded

- (b) Data cache — caches data for faster access; instructions on this path go to the decoder, not through a data cache

- (d) Program counter — holds the address of the next instruction, not the instruction itself

Key rule: Distinguish what holds an address (program counter) from what holds the instruction (instruction register) from what holds values being computed (accumulator).

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