ITPEC FE Morning October 2022 Question 11
There is a 32-bit microprocessor with 32-bit external data bus, driven by 64 MHz input clock, and the processor takes 8 input clock cycles to complete 1 bus cycle. What is the theoretical maximum data transfer rate in megabytes per second (MB/s) for the external data bus of the processor?
Explanation
32 MB/s — convert the clock to bus cycles, then multiply by the bus width in bytes.
- •Bus cycle rate: 64 MHz ÷ 8 = 8 million bus cycles per second
- •Bus width: 32 bits = 4 bytes per bus cycle
- •Transfer rate: 8 × 4 = 32 MB/s
Answer (b)
Why not others:
- •(c) 256 — either uses the raw 64 MHz clock as the bus cycle rate, 64 × 4, ignoring that one bus cycle takes 8 clock cycles, or multiplies 8 million bus cycles by 32 bits and stops at 256 Mbit/s without converting to bytes
- •(a) 3 and (d) 320 — a factor-of-ten slip either side of 32
Key rule: Divide the input clock by the number of clock cycles per bus cycle before multiplying, and convert the bus width from bits to bytes.
Computer Component · AI-written, may contain errors
This question comes from an official ITPEC past paper. ITPEC Practice is an independent study tool and is not affiliated with ITPEC. See the official FE past-paper collection or Report an issue.