ITPEC FE Morning October 2021 Question 13

Pipeline architecture — divides each instruction into stages (fetch, decode, execute) and overlaps them.

While instruction 1 is in the decode stage, instruction 2 is already in fetch — like an assembly line.

Why not others:
- (a) Multicore — multiple independent cores, not about overlapping stages
- (c) RISC — simplified instruction set; often uses pipelining, but is not the concept itself
- (d) VLIW — compiler packs multiple operations into one long instruction word; parallelism decided at compile time

Key rule: "Stages + overlap + shift" = Pipeline.

AI-generated — may contain errors