ITPEC FE Morning October 2021 Question 13
Which of the following is a computer architecture where each instruction is divided into multiple stages (e.g., fetch, decode, and execute) in the processor and multiple functional units execute two or more instructions in parallel by slightly shifting execution stages of the instructions?
Explanation
Pipeline — each instruction is split into stages, and while one instruction is being decoded the next is already being fetched, like an assembly line.
With fetch, decode and execute stages, a new instruction can enter every cycle once the pipeline fills, so up to three instructions are in progress at once, each one stage behind the previous one. That staggered overlap is what the question describes.
Answer (b)
Why not others:
- •(a) Multicore — several complete processor cores on one chip, each running its own instruction stream; the parallelism is between cores, not staggered stages within one
- •(c) RISC — an instruction-set style of simple, fixed-length instructions; it makes pipelining easy but is not the overlapping technique itself
- •(d) VLIW — the compiler packs several independent operations into one very long instruction that the units execute at the same time, not shifted by a stage
Key rule: Pipelining overlaps the stages of consecutive instructions in time; VLIW and superscalar issue several operations in the same cycle; multicore duplicates whole processors.
Computer Component · AI-written, may contain errors
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