ITPEC FE Morning October 2023 Question 12

Topic: Computer ComponentAlso asked in April 2026

Which of the following is an appropriate CPU operation associated with cache memory?

a)When a cache hit occurs, the CPU fetches data from ROM.b)When a cache hit occurs, the CPU fetches data from the main memory.c)When a cache miss occurs, the CPU fetches data from the cache memory.d)When a cache miss occurs, the CPU fetches data from the main memory.

Explanation

On a cache miss the CPU fetches from main memory — a miss means the data is not in the cache, so the next level down supplies it.

•Cache hit: the data is in the cache and is read from there; main memory is not accessed
•Cache miss: the data is absent, so the CPU reads it from main memory and usually copies that block into the cache for later accesses

Answer (d)

Why not others:

•(a) — a hit is served from the cache; ROM holds firmware and plays no part in caching
•(b) — going to main memory on a hit would remove the point of having a cache
•(c) — a miss means the data is not in the cache, so it cannot be fetched from there

Key rule: A hit is served by the cache and a miss by the slower level below it; an option pairing hit with main memory, or miss with the cache, has the two inverted.

Computer Component · AI-written, may contain errors

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