ITPEC FE Morning April 2023 Question 21

Exclusive OR (XOR) — the four NAND gates in this arrangement are the standard way to build XOR from NAND gates only.

Label the gate outputs: P is the NAND of A and B; Q is the NAND of A and P; R is the NAND of P and B; Y is the NAND of Q and R. A NAND output is 0 only when both its inputs are 1.

Y is 1 exactly when the inputs differ, which is XOR.

Answer (c)

Why not others:

• •(a) OR — gives 1 when both inputs are 1, but there P = 0 forces Q = R = 1 and the circuit outputs 0.
• •(b) AND — gives 1 only for inputs 1 and 1, the very row where the circuit gives 0.
• •(d) NOR — gives 1 for inputs 0 and 0, but there P = Q = R = 1 and the circuit outputs 0.

Key rule: To identify a gate network, label every internal output and fill the four-row truth table; the rows where both inputs are equal usually separate the candidates.

Hardware · AI-written, may contain errors