ITPEC FE Morning April 2023 Question 22
At the rising edge of the clock signal, the content of an 8-bit serial-in parallel-out shift register is shifted upward, while positive logic data is simultaneously read into the least significant bit. The value is fixed at the rising edge of a strobe. When the results of an observation of each signal’s waveform are as shown in the diagram below, which of the following is the value of the shift register after it is fixed? Here, numeric values are represented in hexadecimal.
Explanation
8D — the strobe latches the register just before the 10th clock edge, so it holds the bits sampled at edges 2 to 9.
At the ten rising clock edges the Data line reads 1, 1, 0, 0, 0, 1, 1, 0, 1, 1. The strobe rises before the 10th edge, so only 9 shifts have happened when the value is fixed. Each shift moves the contents one place toward the MSB and puts the new bit in the LSB, so the 8-bit register keeps the last 8 bits sampled, edges 2 to 9, the oldest in the MSB; the bit from edge 1 has been shifted out.
- •Edges 2 to 9:
1000 1101 - •
1000= 8 and1101= D, giving 8D
Answer (b)
Why not others:
- •(d) C6 —
1100 0110, the bits from edges 1 to 8: stops one clock too early, although the strobe comes after the 9th edge. - •(c) B1 —
1011 0001, the right eight bits in reverse order, as if new bits entered at the MSB and the register shifted downward. - •(a) 63 —
0110 0011, edges 1 to 8 in reverse order: both mistakes together.
Key rule: Count only the clock edges that occur before the latch signal, and follow the shift direction: when a register shifts toward the MSB, the oldest surviving bit ends up in the MSB.
Hardware · AI-written, may contain errors
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