ITPEC FE Morning April 2023 Question 22

Serial-In Parallel-Out Shift Register — read data bits at each clock rising edge.

An 8-bit SIPO shift register shifts content upward (toward MSB) and reads Data into LSB at each rising edge of Clock. The value is fixed at the rising edge of Strobe.

Reading Data at each Clock rising edge:
- Edge 1: Data = 1
- Edge 2: Data = 0
- Edge 3: Data = 0
- Edge 4: Data = 0
- Edge 5: Data = 1
- Edge 6: Data = 1
- Edge 7: Data = 0
- Edge 8: Data = 1

Register after 8 shifts: 10001101

• •First bit entered (1) is now MSB after 7 subsequent shifts
• •Last bit entered (1) sits in LSB

Convert to hex:
- 1000 = 8
- 1101 = D
- Result: 8D

Why not others:
- (a) 63 (01100011) — incorrect waveform reading
- (c) B1 (10110001) — incorrect waveform reading
- (d) C6 (11000110) — reversed or misread data values

Key rule: In a SIPO register, the first bit entered ends up in the MSB after all shifts complete. At each Clock rising edge, draw a vertical line to the Data signal and carefully determine HIGH (1) or LOW (0). One misread bit changes the entire hex result.

AI-generated — may contain errors