ITPEC FE Morning April 2021 Question 21
ITPEC FE Morning April 2021 — Question 21 of 80
Half Adder Gate Combination — identify the two logic gates in a half adder circuit.
A half adder adds two single-bit binary inputs x and y, producing:
- z (sum) = x XOR y
- c (carry) = x AND y
Truth table:
| x | y | z (XOR) | c (AND) |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
Why not others:
- (b) AND + OR — AND outputs 0 when inputs differ, so sum would be wrong
- (c) NAND + NOR — inverted outputs, does not match binary addition
- (d) NOR + XOR — NOR for sum gives wrong results (1 when both inputs are 0)
Key rule: Half adder = XOR (sum) + AND (carry). Full adder extends this by adding a carry-in input.
AI-generated — may contain errors
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