ITPEC FE Morning April 2018 Question 22
The half adder in the diagram below adds two (2) single-digit binary numbers x and y, and produces z (the first digit of the sum) and c (the carry bit) as output. Which of the following is the appropriate combination of gate devices A and B?
Explanation
XOR for A, AND for B — gate A produces the sum digit z and gate B the carry c, so read each output off the addition table.
Adding two single binary digits gives four cases: 0 + 0 = 00, 0 + 1 = 01, 1 + 0 = 01, 1 + 1 = 10.
- •First digit z: 0, 1, 1, 0. It is 1 exactly when the inputs differ, which is exclusive OR.
- •Carry c: 0, 0, 0, 1. It is 1 only when both inputs are 1, which is AND.
Answer (a)
Why not others:
- •(b) AND, OR — AND as the sum gives 0 for 0 + 1, where z must be 1, and OR as the carry gives a carry for 0 + 1, where there is none
- •(c) NAND, NOR — both gates output 1 for 0 + 0, so the circuit would report a sum digit and a carry when adding nothing
- •(d) NOR, XOR — NOR gives z = 1 for 0 + 0, and XOR as the carry gives 1 for 0 + 1 but 0 for 1 + 1, the opposite of a carry
Key rule: Write the addition table and read each output column as a gate: 1 when the inputs differ is XOR, 1 only when both are 1 is AND.
Hardware · AI-written, may contain errors
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