ITPEC FE Morning April 2018 Question 22

Half Adder Gate Combination — identify XOR and AND gates in a half adder circuit.

A half adder adds two single-bit inputs x and y, producing:

• •z (sum) = x XOR y — output is 1 when inputs differ
• •c (carry) = x AND y — output is 1 only when both inputs are 1

Verification with all input pairs:

• •0 + 0: XOR = 0, AND = 0 → sum = 00 ✓
• •0 + 1: XOR = 1, AND = 0 → sum = 01 ✓
• •1 + 0: XOR = 1, AND = 0 → sum = 01 ✓
• •1 + 1: XOR = 0, AND = 1 → sum = 10 ✓

Why not others:
- (b) AND / OR — AND gives carry correctly, but AND for sum would output 1 only when both are 1
- (c) NAND / NOR — inverted logic; NAND outputs 0 only when both inputs are 1
- (d) NOR / XOR — NOR outputs 1 only when both inputs are 0, incorrect for sum

Key rule: Half adder = XOR (sum) + AND (carry). Full adder extends this with a carry-in input.

AI-generated — may contain errors