ITPEC IP October 2022 Question 11

Cache memory reduces the effective access time of main memory — a small, fast memory between the CPU and main memory keeps copies of the data the CPU is using.

Main memory (DRAM) is much slower than the CPU. Cache memory (SRAM) holds data and instructions the CPU has just used or is likely to use next. On a hit the CPU reads at cache speed; only on a miss does it wait for main memory. With hit ratio h, cache access time C and main memory access time M, the effective access time is h × C + (1 − h) × M.

For example, with h = 0.9, C = 10 ns and M = 100 ns: 0.9 × 10 + 0.1 × 100 = 19 ns instead of 100 ns.

Answer (b)

Why not others:

• •(a) — cache is far smaller than main memory (megabytes against gigabytes), because fast SRAM is expensive; it holds only a copy of part of main memory
• •(c) — a larger main memory is no faster; the speed gap between the CPU and main memory remains, so the cache helps just as much
• •(d) — the hardware decides automatically what the cache holds, keeping recently used data; the user cannot make programs resident in it

Key rule: The higher the hit ratio, the closer the effective access time comes to cache speed; programs keep reusing nearby data (locality), which is why a small cache achieves a high hit ratio.

Computer Component · AI-written, may contain errors