IPA FE Subject A 2024 Question 3
A question IPA Japan published in 令和６年度 基本情報技術者試験 科目A 公開問題 問3, translated into English. ITPEC is based on the same exams.
In the configuration shown in the figure, there are two types of CPUs, X and Y, which differ only in the access times of the cache memory and the main memory as shown in the table, and are the same in the other conditions.
When a certain program was executed on CPU X and on CPU Y, the processing times of both were equal. In this case, what is the hit ratio of the cache memory? Here, there is no influence from processing other than that of the CPU.
Figure Configuration
Table Access times
Unit: nanoseconds
Explanation
0.90 — set the effective access times of the two CPUs equal and solve for the hit ratio.
With hit ratio h, the effective access time is h × cache time + (1 − h) × main memory time:
- •CPU X: 40h + 400(1 − h) = 400 − 360h
- •CPU Y: 20h + 580(1 − h) = 580 − 560h
- •Equal: 400 − 360h = 580 − 560h, so 200h = 180 and h = 0.9
Check: both come to 0.9 × 40 + 0.1 × 400 = 76 ns and 0.9 × 20 + 0.1 × 580 = 76 ns. The cache and main memory sizes in the figure are not needed.
Answer (b)
Why not others:
- •(a) 0.75 — CPU X then takes 130 ns and CPU Y 160 ns: Y’s slower main memory weighs more
- •(c) 0.95 and (d) 0.96 — at these ratios Y’s faster cache wins: 58 ns against 48 ns, and 54.4 ns against 42.4 ns
Key rule: Effective access time = h × cache time + (1 − h) × memory time, where a miss costs the main memory time.
Computer Component · AI-written, may contain errors
This question comes from the past questions IPA Japan publishes, translated into English by ITPEC Practice. ITPEC Practice is an independent study tool and is not affiliated with IPA or ITPEC. See the original paper (PDF) or Report an issue.