IPA FE Subject A 2023 Question 3

Main memory split into independently operating groups that are accessed in parallel — memory interleaving overlaps memory accesses to hide the main memory's cycle time.

After each access a memory module needs time before it can be accessed again (its cycle time), so successive reads from one module wait for each other. Interleaving divides the main memory into banks that operate independently and gives consecutive addresses to different banks: address 0 to bank 0, address 1 to bank 1, and so on. Successive addresses, as in sequential reads of instructions or arrays, then go to different banks whose accesses run in parallel, so the effective transfer speed rises.

Answer (d)

Why not others:

• •(a) — describes DMA (direct memory access): a DMA controller moves data between main memory and I/O devices, or within main memory, without the CPU
• •(b) — describes the write-back method of a cache: writes stay in the cache and reach main memory only when the data is pushed out of the cache
• •(c) — describes cache memory itself, which keeps a copy of part of main memory to narrow the speed gap between the CPU's registers and main memory

Key rule: Interleaving: parallel banks of main memory; cache: a fast copy of part of main memory; write-through or write-back: when cache writes reach main memory; DMA: transfers that bypass the CPU.

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