ITPEC FE Subject A October 2025 Question 16
ITPEC FE Subject A October 2025 — Question 16 of 60
Logic Gate Equivalence — simplify a multi-gate circuit to ¬A · B.
The circuit uses NOT, NAND/NOR combinations that reduce to ¬A · B.
Truth table for ¬A · B:
| A | B | ¬A | Y = ¬A · B |
|---|---|---|---|
| 0 | 0 | 1 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 1 | 1 | 0 | 0 |
Why not others:
- (a) A · B — would be 1 at (1,1)
- (c) A · ¬B — would be 1 at (1,0)
- (d) ¬A · ¬B — would be 1 at (0,0)
Key rule: When a complex circuit has only 2 inputs, build all 4 truth table rows and match against the answer choices. Faster than tracing gates if gate shapes are ambiguous.
AI-generated — may contain errors
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