ITPEC FE Subject A October 2024 Question 16
A graphical symbol for the 2-to-1 MUX (multiplexer) and its truth table are shown in the figure below. The MUX has two data inputs (I0, I1), one select-line (S) and one output (Z). If the select line is S=0, then the output Z is switched to input I0, whereas if a select line is S=1, then the output Z is switched to input I1.
Which of the following is a logic gate that is equivalent to the circuit implemented with the 2-to-1 MUX below?
Explanation
XOR — the MUX outputs X2 when X1 = 0 and NOT X2 when X1 = 1, which is exactly exclusive OR.
The select line is X1, input I0 is X2 and input I1 is X2 inverted:
The output is 1 exactly when the two inputs differ: XOR.
Answer (d)
Why not others:
- •(a) AND — gives 0, 0, 0, 1; it outputs 0 for X1 = 0, X2 = 1, where the MUX passes X2 = 1 through
- •(b) NAND — gives 1, 1, 1, 0; it outputs 1 when both inputs are 0, where the MUX passes X2 = 0
- •(c) OR — gives 0, 1, 1, 1; it outputs 1 when both inputs are 1, where the MUX outputs NOT X2 = 0
Key rule: Read a MUX circuit by writing the output for each value of the select line; “pass the input when the control is 0, invert it when the control is 1” is XOR, a controlled inverter.
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