ITPEC FE Subject A April 2024 Question 16
ITPEC FE Subject A April 2024 — Question 16 of 60
Logic Gate Equivalence — simplify a two-stage gate circuit into one gate.
Original circuit: two gates in cascade producing f(x, y, z).
The equivalent single gate is a 3-input NAND: f = ¬(x · y · z) — answer (d).
NAND outputs 0 only when all inputs are 1; otherwise outputs 1.
Why not others:
- (a) AND(x, y, z) — no inversion on output
- (b) Inverts y and z at input — changes the logic incorrectly
- (c) Two-stage with partial inversion — not equivalent to full 3-input NAND
Key rule: A NAND cascade (NAND feeding into another gate with correct topology) can often simplify to a single multi-input NAND gate. Always verify with truth table when unsure.
AI-generated — may contain errors
The original exam layout is preserved in the image so diagrams, formulas, tables, and code remain accurate.
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