ITPEC FE Morning October 2022 Question 20

Half Adder Logic Circuit — identify the correct gate combination for a half adder.

A half adder adds two single-bit inputs (A, B) and produces:

• •S (Sum) = A XOR B — outputs 1 when inputs differ
• •C (Carry) = A AND B — outputs 1 only when both inputs are 1

Truth table:

Correct answer: (c) — XOR gate for S, AND gate for C.

Why not others:
- (a) — uses OR for S (fails at A=1, B=1 → gives S=1 instead of 0)
- (b) — uses AND for S and XNOR for C (swapped and inverted)
- (d) — uses OR for S (same problem as (a))

Key rule: Half adder = XOR + AND. XOR has an extra curved line at the input side compared to OR. Full adder extends this with a carry-in input.

AI-generated — may contain errors