ITPEC FE Morning October 2022 Question 20

Question

A half adder is a logic circuit that performs the addition of two single-bit binary numbers and outputs the sum and carry. The truth table of a half adder is shown in the table below. Which of the following is an appropriate logic diagram of the half adder?

Inputs | Inputs | Outputs | Outputs
A | B | C (Carry) | S (Sum)
0 | 0 | 0 | 0
0 | 1 | 0 | 1
1 | 0 | 0 | 1
1 | 1 | 1 | 0

Accepted Answer

c) [Figure: Inputs A and B each branch to two gates: the upper gate is an XOR gate whose output is S; the lower gate is an AND gate whose output is C.]

Answer

a) [Figure: Inputs A and B each branch to two gates: the upper gate is a NOR gate whose output is S; the lower gate is an AND gate whose output is C.]

Answer

b) [Figure: Inputs A and B each branch to two gates: the upper gate is an AND gate whose output is S; the lower gate is a NOR gate whose output is C.]

Answer

d) [Figure: Inputs A and B each branch to two gates: the upper gate is an AND gate whose output is S; the lower gate is an XOR gate whose output is C.]

Explanation