ITPEC FE Morning October 2019 Question 24

Circuit (b) — it builds the AND and the OR from NAND gates and keeps the final NAND, so it computes the same F = A•B•(B + C).

The original feeds A•B and B + C into a NAND gate. Each part has a NAND form:

• •NOT: a NAND with both inputs tied, X•X = X
• •AND: a NAND followed by a NOT, A•B = A•B
• •OR: a NAND of the inverted inputs, B•C = B + C by De Morgan's law

In (b), gates 1 and 2 give A•B, gates 3 to 5 give B + C, and gate 6 is the output NAND. By absorption A•B•(B + C) = A•B, so F = A•B: 0 only when A = B = 1.

Answer (b)

Why not others:

• •(a) — gates 1 to 3 make A•B•B = A•B + B = B, an OR of the wrong signals, and gates 4 and 5 just return C; F = B•C, which gives 1 for A = B = 1, C = 0
• •(c) — gates 1 to 3 again reduce to B, and gates 3 to 5 make B•C, an AND where an OR is needed; F = B•C, wrong for the same input
• •(d) — the AND half is right, but gates 3 to 5 make B•C + C = C instead of B + C; F = A•B•C, which gives 1 for A = B = 1, C = 0

Key rule: With NAND gates only, AND is NAND then NOT, and OR is NAND of the inverted inputs; label each gate's output and test one input row that separates the candidates.

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