IPA FE Subject A 2026 Question 6
A question IPA Japan published in 令和８年度 基本情報技術者試験 科目A 公開問題 問6, translated into English. ITPEC is based on the same exams.
When signals are input to A and B of the circuit in the figure, which of the following is the appropriate timing chart of the signal that is output to Y?
Explanation
Y is 1 only while A and B are both 0 — the four NAND gates together form a NOR gate.
- •A NAND gate with its two inputs tied together is a NOT gate, so the first two gates output NOT A and NOT B.
- •The third gate gives NOT(NOT A AND NOT B) = A OR B, by De Morgan’s law.
- •The fourth gate, its inputs tied, inverts that: Y = NOT(A OR B), a NOR.
Check the seven time slots of (b): A = 0, 1, 0, 0, 0, 1, 0 and B = 0, 0, 0, 1, 0, 1, 0 give Y = 1, 0, 1, 0, 1, 0, 1, which is the Y drawn.
Answer (b)
Why not others:
- •(a) — Y is 0 only where both inputs are 1: a single NAND of A and B
- •(c) — Y is 1 where exactly one input is 1 and 0 where both are: XOR
- •(d) — Y is 1 only where both inputs are 1: AND
Key rule: A NAND with tied inputs is a NOT; reduce the circuit gate by gate with De Morgan’s laws, then check the time slots where the options differ.
Hardware · AI-written, may contain errors
This question comes from the past questions IPA Japan publishes, translated into English by ITPEC Practice. ITPEC Practice is an independent study tool and is not affiliated with IPA or ITPEC. See the original paper (PDF) or Report an issue.